1. Field of Invention
The present invention relates to a method of reducing floating body effect of SOI (silicon on insulator) MOS (metal oxide semiconductor) device, more particularly to method of reducing floating body effect of SOI MOS device via a large tilt implantation, which belongs to semiconductor manufacturing field.
2. Description of Related Arts
With the size of the VLSI continuing to shrink, a series of problems arise regarding to material technology, device theory, device structure and manufacturing process. In order to solve these problems, a serial of new techniques, such as strained channel material, high K gate dielectric and metal gate electrode material and so on, are developed in 45 nm process or below. SOI, silicon on insulator, is one of the main stream techniques of the 21st century. SOI overcomes the drawbacks of the silicon material due to its unique structure, so as to become a main stream technique of the VLSI circuit of high speed, low consumption, high integration and high reliability.
SOI MOS is divided into a partially depleted SOI MOS (PDSOI) and a fully depleted SOI MOS (FDSOI) according to whether the body region of the active area is fully depleted or not. Usually, the silicon film on top of the FDSOI is very thin, thin film SOI silicon costs high, and the threshold voltage of the FDSOI is hardly controlled. Therefore, the PDSOI is commonly used.
The body region of the active area of PDSOI is not fully depleted, so that the body region is suspended, and the charge produced via collision and ionization can not be transferred quickly, which will result in the floating body effect. As for SOI NMOS channel, the electrons in the drain region are collided and ionized to produce electron-hole pairs. The holes flow to the body region, and the floating effect of SOI MOS result in the accumulation of the holes in the body region, so as to raise the electric potential of the body region. Therefore, the threshold voltage of the SOI NMOS is lower and the drain current increases, which is called Kink effect Kink effect has many adverse effects to the performance and reliability of the device and circuit, so that the kink effect should be controlled in the design of the device. As for SOI PMOS, the ionization rate is low and the electron-hole pairs produced by collision and ionization are much lower than that of SOI NMOS, so the kink effect is not obvious.
In order to overcome the drawbacks of the SOI NMOS, a body contact method is used to connect the body to the source or the ground. As shown in FIGS. 1a and 1b, the P+ implantation area formed at one side of the T-shaped gate is connected to the P type body region under the gate region. When the MOS device is operating, the carriers accumulated in the body region are released through P+ passage so as to lower the electrical potential of the body region. The drawbacks of the method are that the process is complex, the parasitic effect is increased, part of the electrical performance is lowered and the area of the device is increased.
Therefore, there is a need to develop a new method to reduce the floating body effect of MOS.